In wafer edge exposure apparatuses in which an edge of a resist coated wafer is exposed, various photolithography steps are used. FIG. 1 shows a flowchart representing a photolithography processing flow 100 to be effected for a certain layer (called here an “ith layer”) in connection with a related art semiconductor device manufacturing method. During the processing shown in FIG. 1, a resist is applied over or coated onto a semiconductor wafer by a spin coating method (step 102).
After the resist has been applied to the wafer surface, it undergoes a soft bake or pre-exposure bake to drive off most of the solvent in the resist to improve adhesion, promote resist uniformity on the wafer, and achieve better linewidth control during etching (step 104). Step 106 is alignment and exposure. The mask is aligned to the correct location of the resist-coated wafer. Once aligned, the mask and wafer are exposed to controlled light (e.g., UV light) to transfer the mask image to the resist-coated wafer.
The semiconductor wafer is further subjected to wafer edge exposure (WEE) processing performed by an edge exposure apparatus (step 108) and followed by a post exposure bake (step 110). In step 108, the edge exposure apparatus is used for exposing an edge of the wafer over a desired width (e.g., 1 mm or 2 mm).
When having finished undergoing the pattern exposure processing and edge exposure processing, the semiconductor wafer is subjected to a process of developing a resist (step 112). As a result of the processing being performed, the resist located along the edge of the wafer is removed over a desired width (e.g., 1 mm or 2 mm), and the resist on the semiconductor wafer is patterned into a desired pattern.
There is then performed processing for etching the semiconductor wafer while the thus patterned resist is taken as a mask or implanting impurities into the semiconductor wafer (step 114).
In wafer edge exposure, foreign substances or contaminants such as resist residues, for example can sometimes form on the backside of the wafer. These contaminants can cause exposure problems. FIG. 2a depicts a situation in which an in-focused image is transferred to resist coated wafer 200. An exposure light 204a transfers a mask pattern 202 to a lens 206 which then produces a focused light 204b onto the resist coated wafer 200. In FIG. 2b, however due to a contaminant 240 on the backside of the resist coated wafer 200, the light 204b becomes out of focus and therefore mask pattern 202 cannot faithfully be transferred to the resist coated wafer 200. Contaminants on the backside of wafers can lead to yield and reliability problems.